1. Field of the Invention
The present invention relates to a computer system, more specifically, to timing control with respect to an external memory device.
2. Description of the Related Art
Rapid progresses in semiconductor integration technologies in recent years have enabled a central processing unit (CPU) of a computer to be integrated into a single semiconductor chip. Further, attempts for integrating a peripheral interface and a memory control circuit into the single chip are also ongoing. In terms of integrating an entire computer system into a single chip, such technologies are referred to as “system on a chip (SOC)” technologies or SOC products.
A memory device for storing instructions to be first executed in start-up processing of a computer after power-on is generally referred to as a boot read only memory (ROM). The boot ROM is required to have characteristics that instruction codes are recordable thereon in advance and that contents can be retained when the power is off. The boot ROM stores different instruction sequences depending on the product to which the CPU is applied. Accordingly, the boot ROM is usually designed as an external element of a CPU chip.
Semiconductor elements suitable for use in the boot ROM include a variety of elements such as a mask ROM, an erasable and programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash ROM, and the like. Read time for the stored contents also varies depending on types of elements, price ranges and specifications of products. Accordingly, it is a common practice in a CPU chip integrating a boot ROM interface that several patterns of booting modes are predicted in advance and the CPU chip is set up so as to effectuate selection in line with product features or user orientation.
Normally, several signal lines are utilized for judging as to which type of the boot ROM is used, and identification and read time of the boot ROM is selected in the event of power-on or resetting, because the instructions stored in the boot ROM are instructions to be executed in the first place. As there is no instruction sequence executable beforehand, it is impossible to select read time by software.
Another judging method is to assume the slowest read time of a predictable ROM. In this method, the CPU chip operates in the slowest operating speed immediately after resetting and the operating speed for the ROM is set again depending on the instruction retrieved at that stage.
However, the above-described computer system involves the following problems.
1) An SOC product in recent years requires numerous terminals as a result of mounting various peripheral interfaces, peripherals themselves and memory interfaces in one chip. Moreover, although an operating frequency of each terminal is not as high as a frequency of an internal circuit, yet the operating frequency is increasing every year. Accordingly, an expensive package and terminals applicable to high frequencies are becoming indispensable. Generally, a terminal structure of a package depends on the maximum frequency of an applicable chip. In other words, the package structure does not reflect the frequency to be applied actually to the terminal. This is due to the fact that modification of the terminal structure depending on an execution frequency incurs cost increases to the contrary.
Therefore, in the above-described method of using several signal lines, it is necessary to allocate terminals for signals which operates only after resetting such as signals for setting up read-out speed for the boot ROM. Accordingly, there is a problem of incurring a cost increase as the number of terminal increases.
2) Meanwhile, in the method of assuming the slowest operating speed, there is a problem of low speed in executing the instructions before setting up the operating speed. Although this may rarely constitute a critical problem in an real chip, it will constitute considerable loads in the event of logic simulation for verifying operations and functions because the instruction sequence on the boot ROM is executed in every iteration of the logic verification.
Normally, logic quality of an SOC semiconductor element tends to be enhanced in response to an effort spent for the logic verification. Accordingly, reduction in the amount of the logic verification executable in a unit time period incurs a problem of difficulty in securing sufficient logic quality. On the contrary, if a sufficient verification amount is sought, then simulation time is increased and a cost increase is thereby incurred.
Furthermore, if the read time or timing thereof varies in excess of a expected range for the boot ROM element, then the method cannot be applied to such a product. Resultantly, there is also a problem of shortening a life cycle of the product.